The present invention relates to a register setting method, and more particularly, to a method of setting a resistor for storing data for controlling a variety of operational specifications of a device, and a semiconductor device.
A semiconductor device typically has a large number of operation modes so that an optimal operation mode for a user""s system is set in the semiconductor device. The semiconductor device comprises a mode register for storing an operation mode setting value. The semiconductor device operates based on the operation mode setting value stored in the mode register.
The mode register setting value is generally supplied from an external device in response to a mode register set (MRS) command. The MRS command is a command for initially setting the operation mode of the semiconductor device. The MRS command is supplied from a system in response to a power-on of the system or a released reset signal associated with a system reset. More specifically, in accordance with the MRS command, the mode register in the semiconductor device stores set values for operation conditions (hereinafter called the xe2x80x9coperation condition informationxe2x80x9d), for example, a CAS latency (2 clocks, 3 clocks, or 4 clocks), an addressing mode (sequential mode or interleave mode), burst (burst length: 0, 2, 4, or 8), and the like.
FIG. 1 is a schematic block circuit diagram of a semiconductor device 100 according to a first prior art example.
The semiconductor device 100 is, for example, an EEPROM or a flash memory, i.e. a non-volatile semiconductor memory device. A mode register 11 stores a previously set initial value for the operation condition information (hereinafter called the xe2x80x9cdefault valuexe2x80x9d) as the semiconductor device 100 is powered on. The default value is set by a ROM which stores information, for example, by cutting a predetermined element with a laser, or by a latch circuit which is set to have a constant value by a power supply. The mode register 11, in response to a start signal stt, supplies a memory control circuit 12 with a control signal including the stored default value. The memory control circuit 12, in response to the control signal, controls peripheral circuits (for example, an input/output circuit). The semiconductor device 100 operates in accordance with the default value.
A MRS control circuit 13 generates a set signal in response to a MRS command, and supplies the set signal to the mode register 11. The MRS command is specified by a combination of levels of a plurality of control signals. Specifically, when a command generated by decoding a plurality of control signals is an MRS command, the MRS control circuit 13 supplies the mode register 11 with a set signal based on an address (ADD) signal. The mode register 11 stores a variety of set values in response to the set signal, and generates a memory control signal in accordance with the set values, and supplies a memory control signal to the memory control circuit 12. In this event, the semiconductor device 100 operates in accordance with newly set operation condition information.
FIG. 2 is a diagram illustrating a sequence of operations in the first prior art example including the user""s system.
As the device 100 is powered on, a start signal stt is generated within the device 100 (step S1), and the mode register 11 is set to a default value (step S2). At this time, information in the mode register 11 is established (step S3).
Next, it is determined whether or not an operation condition (mode) has been changed (step S4). When the operation condition is not changed, the mode register 11 supplies a memory control signal to the memory control circuit 12 (step S5). In response to the memory control signal, the memory control circuit 12 operates, causing the device 100 to perform an operation such as read/write.
Afterwards, the mode register 11 is rewritten by an MRS command for adapting the operational specifications of the device to system""s operational specifications on the user side. When the operation condition is changed, a mode control signal is generated (step S6), and the MRS control circuit 13 decodes a command to generate a register set signal which is supplied to the mode register 11 (step S7). Thus, new operation condition information is set in the mode register 11 (step S3).
The mode register 11 is a memory having a fast write and read operation so that its setting can be immediately changed, and is typically implemented by a volatile memory. Therefore, a set value must be written into the mode register 11 by an external device each time a system, equipped with the semiconductor device 100 including the mode register 11, is powered on or reset. The rewriting results in a longer start-up time from power supply to the device to the actual operation of the device adapted to new specifications.
FIG. 3 is a schematic block circuit diagram of a semiconductor device 200 according to a second prior art example.
The semiconductor device 200 includes a load register 22 for transferring a set value (operation condition information) to a mode register 21. The load register 22 has a rewrite control circuit 22a and a non-volatile RAM 22b. The control circuit 22a receives a rewrite command (LRW command: Load Register Write command) from an external device. The control circuit 22a rewrites the contents of the non-volatile RAM 22b in response to the LRW command.
The load register 22, in response to a start signal stt, transfers the set value stored in the non-volatile RAM 22b to the mode register 21. The mode register 21 generates a memory control signal in accordance with the set value, and supplies the memory control signal to a memory control circuit 23.
Since the semiconductor device 200 includes the non-volatile RAM 22b of the load register 22, the set value does not need to be set again in the mode register 21 each time the system is powered on or the system is reset.
FIG. 4 is a diagram illustrating a sequence of operations in the second prior art example.
As the device 200 is powered on, a start signal stt is generated within the device 200 (step S11), and an initial value is set in the load register 22 in response to the start signal stt (step S12). The load register 22 loads the initial value into the mode register 21 (step S13) to establish initial information in the mode register 21 (step S14).
Next, it is determined whether or not the operation condition (mode) has been changed (step S15). When the mode is not changed, the mode register 21 supplies a memory control signal to the memory control circuit 23 (step S16). The memory control circuit 23 operates in response to the memory control signal, causing the device to perform an operation such as read/write.
Afterwards, the mode register 21 is rewritten by an MRS command for adapting the operational specifications of the device to the system""s operational specifications of the user. When the mode is changed, a mode control signal is generated (step S17). An MRS control circuit 24 decodes a command to generate a register set signal which is supplied to the mode register 21 (step S18). At this time, new operation condition information is set in the mode register 21 (step S14).
As the device 200 is once shut off, the set value (initial value) of the mode register 21, after the device 200 is again powered on is loaded again from the load register 22 and stored in the mode register 21.
When the content of the load register 22 is changed, the system generates a rewrite command (LRW command) (step S19). The rewrite control circuit 22a supplies rewrite information to the non-volatile RAM 22b in response to the LRW command (step S20) to rewrite the contents of the non-volatile RAM 22b. Therefore, when the device 200 is powered on at a later time, a new initial value is loaded into the mode register 21. The memory control circuit 23 operates in accordance with the new initial value, causing the device to perform an operation such as read/write.
In the second prior art example, the system only requires a simple program, and improves the overall performance. However, a command must be provided for supplying the load register 22 with register information. This increases the program control step on the system side by one. Also, in a shipment process of the system (board) on the client side, a special write must be performed into the load register 22, causing an increase in the number of steps.
FIG. 5 is a schematic block circuit diagram of a semiconductor device 300 according to a third prior art example.
The semiconductor device 300 includes a load register 25. The load register 25 has a rewrite control circuit 25a and a non-volatile RAM 25b. In response to a start signal stt, the load register 25 stores a register set value in the non-volatile RAM 25b to generate a memory control signal which has a register set value. The memory control signal is supplied to a memory control circuit 26.
The control circuit 25a receives an LRW command from an external device, and rewrites the contents of the non-volatile RAM 25b in response to the LRW command.
Since the semiconductor device 300 includes the non-volatile RAM 25b, the operation mode does not need to be set again when the system is powered on or reset.
FIG. 6 is a diagram illustrating a sequence of operations in the third prior art example.
As the device 300 is powered on, a start signal stt is generated (step S91). In response to the start signal stt, an initial value is set in the load register 25 (step 92). The load register 25 loads the initial value to the memory control circuit 26 (step S93) to establish operation condition information in the memory control circuit 26 (step S94).
When the content of the load register 25 is changed, as the system generates a rewrite command (LRW command) for changing the stored mode data (step S95), the LRW command is supplied to the rewrite control circuit 25a of the load register 25. The control circuit 25a supplies rewrite information to the non-volatile RAM 25b in response to the LRW command (step S96) to rewrite the contents of the non-volatile RAM 25b in accordance with the rewrite information (step S92). Therefore, when the semiconductor device 300 is powered on at a later time, a set value (new initial value) written in the non-voltage RAM 25b is loaded into the memory control circuit 26. Then, the memory control circuit 26 operates in accordance with the new initial value, causing the device to perform an operation such as read/write.
In the third prior art example, the load register 25 loads the mode information in the non-volatile RAM 25b into the memory control circuit 26 in response to the start signal stt. Therefore, even if the contents of the non-volatile RAM 25b are changed by the LRW command, the start signal stt must be generated by powering again or resetting the system in order to reflect the change to the operation of the system. For this reason, the third prior art example has a problem that an extremely long time is required for changing the operation of the system.
It is an object of the present invention to provide a register setting method to facilitate writing of change information into a register which stores operation condition information that defines the operation of a system, and a semiconductor device including the register.
It is another object of the present invention to provide a register setting method and a semiconductor device which readily reflect operation condition information for the device, stored in a non-volatile memory, to a system.
To achieve the above object, the present invention provides a register setting method for setting operation condition information, which defines the operation of a device, in a first register and a second register. The method includes storing first operation condition information in the first register, storing second operation condition information in the second register, changing the first operation condition information, and when the first operation condition information is changed, changing the second operation condition information in accordance with change information for changing the first operation condition information.
A further perspective of the present invention is a register setting method for setting operation condition information, which defines the operation of a device, in a first register including a volatile memory and a second register including a non-volatile memory. The method includes storing first operation condition information in the first register, storing second operation condition information in the second register, changing the second operation condition information, and when the second operation condition information is changed, changing the first operation condition information in the first register substantially at the same time the second operation condition information is changed, in accordance with change information for changing the second operation condition information.
A further perspective of the present invention is a semiconductor device having a plurality of operation modes and adapted to operate in accordance with operation condition information which defines each operation mode. The semiconductor device includes a first register for storing first operation condition information, and a second register connected to the first register for storing second operation condition information. A device control circuit is connected to the first register for controlling the operation of the semiconductor device in accordance with the first operation condition information or the second operation condition information. When the first operation condition is changed, the second register receives a set signal including change information for changing the first operation condition information, and changes the second operation condition information to changed first operation condition information in accordance with the change information.
A further perspective of the present invention is a semiconductor device having a plurality of operation modes and adapted to operate in accordance with operation condition information which defines each operation mode. The device includes a first register for storing first operation condition information, and a change detector connected to the first register for detecting a change in the first operation condition information stored in the first register to generate a detection signal in accordance with the detected change. A second register is connected to the first register and the change detector for storing second operation condition information in response to the detection signal. A device control circuit is connected to the first register for controlling the operation of the semiconductor device in accordance with the first operation condition information or the second operation condition information. The second register receives a second register change signal including change information for changing the first operation condition information, and changes the second operation condition information to changed first operation condition information in accordance with the change information in response to the detection signal.
A further perspective of the present invention is a semiconductor device having a plurality of operation modes and adapted to operate in accordance with operation condition information which defines each operation mode. The device includes a first register including a volatile memory for storing first operation condition information, and a second register connected to the first register and including a non-volatile memory for storing second operation condition information. A device control circuit is connected to the first register and the second register for controlling the operation of the semiconductor device in accordance with the first operation condition information or the second operation condition information. When the second operation condition information is changed, the second register changes the first operation condition information in the first register to changed second operation condition information substantially at the same time the second operation condition information is changed, in accordance with change information for changing the second operation condition information.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.